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FEDL9841-04 Semiconductor
FEDL9841-04 This version: MSM9841 Jul. 2000 Previous version: Jun. 1999
Semiconductor MSM9841
Recording and Playback LSI with Built-in FIFO
This document contains minimum specifications. For full specifications, please contact your nearest Oki office or representative.
GENERAL DESCRIPTION
The MSM9841 is a mono/stereo record and playback LSI with a built-in 1K bit FIFO for easy interface with external systems or non-semiconductor memory. It utilizes multiple record and playback modes, including the new ADPCM2 algorithm, which allows for even higher quality sound reproduction. The record and playback functions of the MSM9841 is controlled by an MCU via 8/16-bit bus interface.
FEATURES
* 16/8-bit bus interface support * FIFO capacity: User-definable (256/512/1024 bits) (buffering time of 32 ms when using 8 kHz sampling frequency, 4-bit ADPCM2/ADPCM, and in monaural playback) * Supports four compression algorithms for record and playback: 4, 5, 6, 7, 8-bit ADPCM2; 4-bit ADPCM; 8; 16-bit PCM; and 8-bit Nonlinear PCM * Sampling frequency: 4.0 kHz, 6.4 kHz, 8.0 kHz, 12.8 kHz, 16.0 kHz, 32.0 kHz* (fosc=4.096 MHz) * Sampling frequency: 22.05 kHz*, 44.1 kHz* (fosc=5.6448 MHz) * For the built-in ADC, set the sampling frequency at 16 kHz or less. * DMA interface support * Volume control (8 steps: 0 dB to -21 dB) * Built-in 14-bit A/D converter * Built-in 14-bit D/A converter * Built-in low pass filter (LPF) : (input side: analog LPF) : (output side: digital LPF) * Power supply voltage: 2.7 V to 5.5 V * Package: 56-pin plastic QFP (QFP56-P-910-0.65-2K) (Product name: MSM9841GS-2K) *note 32 kHz, 22.05 kHz and 44.1 kHz are available only for playback.
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FEDL9841-04 Semiconductor MSM9841
BLOCK DIAGRAM
MOUT LOUT AOUTL AOUTR SG AVDD AGND DVDD DGND
MIN
input side
LPF LIN
ADC
output side
LPF
DAC
DAC
output side
LPF
Volume Controller EMP MID FUL/DREQR CH/DACKR FIFO ADSD DASD SIOCK
ADPCM2/ADPCM/PCM Analyzer ADPCM2/ADPCM/PCM/Non-linear PCM Synthesizer
D15 to D0 WR RD CS D/C BUSY
MCU I/F DMA I/F Timing Controller TEST0 TEST1
DREQL DACKL IOW
IOR
VCK XT XT
RESET
External DAC/ADC I/F
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PIN CONFIGURATION (TOP VIEW)
51 DREQL 50 DACKL
43 SIOCK
42 BUSY 41 D/C 40 CS 39 RD 38 WR 37 FUL/DREQR 36 MID 35 EMP 34 CH/DACKR 33 RESET 32 NC 31 DVDD 30 AVDD 29 AOUTR
48 TEST1
47 TEST0
49 DGND
45 ADSD LOUT 26
D0 D1 D2 D3 NC D4 D5 D6 D7
1 2 3 4 5 6 7 8 9
NC 10 D8 11 D9 12 D10 13 D11 14
NC 15
D12 16
D13 17
D14 18
D15 19
NC 20
DGND 21
AGND 22
MIN 23
MOUT 24
LIN 25
SG 27
44 DASD
52 IOW
46 VCK
53 IOR
56 NC
55 XT
54 XT
NC : No Connection 56-pin plastic QFP
AOUTL 28
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PIN DESCRIPTIONS
Symbol Type Description For 8-bit bus interface, the command allows these pins to be configured to be inputs or outputs to input or output data to and from an external memory. Otherwise, these pins are configured D15-D8 I/O to be inputs only. For 16-bit interface, these pins are a bidirectional data bus to input or output data to and from an external microcontroller and memory. D7-D0 WR RD CS D/C BUSY EMP I/O I I I I O O Birirectional data bus to input or output data and output status to and from an external microcontroller and memory. Write pulse input pin. This pin pulses "L" when command or voice data is input to D15-D0 pins. Read pulse input pin. This pin pulses "L" when status or voice data is output to D15-D0 pins. Accepts write pulse and read pulse when this pin is "L". Does not accept write pulse and read pulse when this pin is "H". Voice data is input or output to and from D15-D0 pins when this pin is "H". Command is input to and status is output from D7-D0 pins when this pin is "L". This pin outputs a "L" level during RECORDING, PLAYBACK or PAUSE. "H" level indicates that there is no data in FIFO memory. Active "H" can be changed to active "L" by command input. "H" level indicates that more than half of the FIFO memory space is filled with data. MID O During playback, voice synthesis starts when MID changes to "H" level. Active "H" can be changed to active "L" by command input. This pin outputs a synchro signal for voice data input/ output when non-use of FIFO is selected. "H" level indicates that FIFO memory is full of data. During playback, this pin is "H" and data FUL/DREQR O cannot be written in FIFO memory. Active "H" can be changed to active "L" by command input. When DMA transfer and stereo playback are selected, "H" level DREQR outputs a signal to request a DMA transfer. Active "H" can be changed to active "L" by command input. When stereo playback is selected and CH is "H", the EMP, MID or FUL pin outputs the status of right FIFO memory. When CH is "L", the EMP, MID or FUL pin outputs the status of left FIFO CH/DACKR I memory. Set this pin to "L" during recording and monophonic playback. When DMA transfer and stereo playback are selected, DACKR is selected. In this case, input a DMA transfer acknowledge signal to DACKR. When DACKR is "L", the IOW signal is accepted. Active "L" can be changed to active "H" by command input. When DMA transfer is selected, "H" level DREQL outputs a signal to request a DMA transfer. DREQL O When stereo playback is selected, "H" level DREQL outputs a signal to request a DMA transfer. Active "H" can be changed to active "L" by command input. Input to DACKL a signal when DMA transfer is permitted by the DMA controller. When DACKL DACKL I is "L", IOR and IOW signals are accepted. When stereo playback is selected, input to DACKL a DMA transfer acknowledge signal for left FIFO memory. Active "L" can be changed to active "H" by command input. If DMA transfer is not used, set this pin to "H" level.
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PIN DESCRIPTIONS
Symbol IOW IOR ADSD DASD SIOCK XT XT VCK RESET TEST0 TEST1 SG MIN LIN MOUT LOUT AOUTL AOUTR DVDD DGND AVDD AGND Type I I I O O I O O I I O I O O O -- -- -- -- Description Write pulse input pin to write external memory data to MSM9841 during DMA transfer. If DMA transfer is not used, set this pin to "H" level. Read pulse input pin to read data of MSM9841 during DMA transfer. If DMA transfer is not used, set this pin to "H" level. 16-bit serial data input pin when external ADC is used. If external ADC is not used, set this pin to "L" level. 16-bit serial data output pin when external DAC is used. Synchronizing clock for 16-bit serial data input/output when external ADC or DAC is used. Oscillator connection pins. When external clock is used, input clock into XT pin and leave XT pin open. Outputs sampling frequency selected at recording or playback. VCK pin is used as a synchronizing signal when external ADC or DAC is used. When this pin is "L" level input, the LSI is initialized. Pins for testing. Set the pins to "L". Analog circuit signal ground output pin. Inverting input pin for built-in OP amplifier. Noninverting input pin is connected to SG (Signal Ground) internally. MOUT is the output of internal OP amplifier to MIN, and LOUT is to LIN. Left analog output pin from built-in LPF. This is the output pin of playback wavefroms, and is connected to the amplifier for driving speakers. Right analog output pin from built-in LPF. This is the output pin of playback wavefroms, and is connected to the amplifier for driving speakers. Digital power supply pin. Insert a minimum 0.1 mF bypass capacitor between this pin and DGND pin. Digital GND pin. Analog power supply pin. Insert a minimum 0.1 mF bypass capacitor between this pin and AGND pin. Analog GND pin.
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ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Input Voltage Storage Temperature Symbol VDD VIN TSTG Condition Ta=25C Ta=25C -- Rating -0.3 to +7.0 -0.3 to VDD+0.3 -55 to +155 Unit V V C
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage Operating Temperature Master Clock Frequency Symbol VDD TOP fOSC Condition DGND=AGND=0V -- -- Min. 4.0 Range 2.7 to 5.5 -40 to +85 Typ. 4.096 Max. 6.0 Unit V C MHz
ELECTRICAL CHARACTERISTICS
DC Characteristics
DVDD=AVDD=2.7 to 5.5V, DGND=AGND=0V, Ta=-40 to +85C Parameter High-level Input Voltage Low-level Input Voltage High-level output Voltage Low-level output Voltage High-level Input Current (*1) High-level Input Current (*2) High-level Input Current (*3) Low-level Input Current (*1) Low-level Input Current (*2) Symbol VIH VIL VOH VOL IIH1 IIH2 IIH3 IIL1 IIL2 Condition -- -- IOH=-40 mA IOL=2 mA VIH=VDD VIH=VDD DVDD=AVDD=4.5 to 5.5 V, VIH=VDD DVDD=AVDD=2.7 to 3.6 V, VIH=VDD VIL=GND VIL=GND DVDD=AVDD=4.5 to 5.5 V, Operating Current consumption IDD fosc=4.096 MHz, whithout load DVDD=AVDD=2.7 to 3.6 V, fosc=4.096 MHz, whithout load At power down, without load Stanby Current consumption IDDS Ta=-40 to +70C At power down, without load Ta=-40 to +85C Min. VDD0.85 -- VDD-0.3 -- -- -- 30 10 -10 -20 -- -- -- -- Typ. -- -- -- -- -- -- 150 50 -- -- 15 10 -- -- Max. -- VDD0.2 -- 0.45 10 20 300 100 -- -- 30 20 10 50 Unit V V V V mA mA mA mA mA mA mA mA mA mA
*1 Applicable to input pins excluding XT pin. *2 Applicable to XT pin. *3 Applicable to TEST0 pin and TEST1 pin.
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CPU INTERFACE EXAMPLES
1) Interface when DMA controler is used (16-bit bus)
Memory M9841
DMA Controller
D15 to D0 DREQL DACKL IOW IOR DREQR DACKR
MCU RD WR CS D/C
Data bus
2) MCU & external memory interface (16-bit bus)
Memory M9841 D15 to D0 DACKL IOW IOR MCU RD WR CS D/C CH EMP MID FUL
Data bus
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PACKAGE DIMENSIONS
(Unit : mm)
QFP56-P-910-0.65-2K
Mirror finish
Oki Electric Industry Co., Ltd.
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin 42 alloy Solder plating (5 mm) 0.43 TYP. 4/Nov. 28, 1996
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. MS-DOS is a registered trademark of Microsoft Corporation.
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Copyright 2000 Oki Electric Industry Co., Ltd.
Printed in Japan
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